A power conversion apparatus is known, which includes a power converter configured by a plurality of semiconductor elements, a gate logic circuit for generating a gate signal for switching on/off the respective semiconductor elements, a gate drive circuit for driving the semiconductor elements, a first transmitting circuit for transmitting the gate signal to the gate drive circuit and a second transmitting circuit for transmitting a feedback signal indicating on/off of the semiconductor elements from the gate drive circuit wherein two fault detecting circuits detect errors based on a logical sum of the gate signal and the feedback signal (for example, Japanese Laid-open Patent Publication No. H07-095761).